Verilog by example : a concise introduction for FPGA design

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Material type: Text

Subject(s):

DDC classification:

Contents:

1. The Tool Flow

2. In and Out

3. Clocks and Registers

4. State Machines

5. Modular Design

6. Memories

7. Managing Clocks

8. I/O Flavors

9. A Taste of Simulation

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Holdings
Item type	Current library	Collection	Call number	Status	Notes	Date due	Barcode	Item holds
Books	IIITD General Stacks	Engineering and Allied Operation	621.39 REA-V (Browse shelf(Opens below))	Available	Gifted by Dr. Prasoon Tiwari		G02850

Total holds: 0

Includes bibliographical references and index.