Practical design verification
Material type: TextPublication details: New York : Cambridge University Press, ©2009Description: xi, 276 p. : ill. ; 26 cmISBN:- 9780521859721
- 621.381 PRA-P
Item type | Current library | Collection | Call number | Status | Date due | Barcode | Item holds | Course reserves |
---|---|---|---|---|---|---|---|---|
Books | IIITD Reference | Electronics and Communication Engineering | REF 621.381 PRA-P (Browse shelf(Opens below)) | Not for loan | 013050 |
Browsing IIITD shelves, Shelving location: Reference, Collection: Electronics and Communication Engineering Close shelf browser (Hides shelf browser)
REF 621.381 PER-D Digital integrated circuits : | REF 621.381 PIL-E Electrical and electronics engineering materials | REF 621.381 POZ-M Microwave engineering | REF 621.381 PRA-P Practical design verification | REF 621.381 RAZ-D Design of analog CMOS integrated circuits | REF 621.381 RAZ-D Design of analog CMOS integrated circuits | REF 621.381 RAZ-F Fundamentals of microelectronics |
Includes bibliographical references and index.
1. Model checking and equivalence checking 2. Transaction-level system modeling 3. Response checkers, monitors, and assertions 4. System debugging strategies 5. Test generation and coverage metrics 6. SystemVerilog and Vera in a verification flow 7. Decision diagrams for verification 8. Boolean satisfiability and EDA applications
Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of formal and simulation-based techniques are covered too, as are more recent research advances including transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT).
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