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Course reserves for Verification and High-Level Synthesis of VLSI Designs

  1. Term: Winter
  2. Department: Electronics & Communication Engineering
  3. Course number: ECE5xx
  4. Instructors:
    • Dr. Sumit Mediratta
Title Item type Location Collection Call number Copy number Status Date due Notes
System verilog assertions and functional coverage : Reference IIITD
Reference
Computer Science and Engineering REF 621.392 MEH-S Available
SystemVerilog for verification : Reference IIITD
Reference
Electronics and Communication Engineering REF 621.392 SPE-S Available
System design with systemC Reference IIITD
Reference
Computer Science and Engineering REF 004.21 GRO-S Available

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