SystemVerilog for verification : a guide to learning the testbench language features

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Holdings
Item type	Current library	Collection	Call number	Status	Date due	Barcode	Item holds	Course reserves
Reference	IIITD Reference	Electronics and Communication Engineering	REF 621.392 SPE-S (Browse shelf(Opens below))	Checked out Not for loan	18/04/2024	010125		Verification and High-Level Synthesis of VLSI Designs WNT

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Includes bibliographical references and index.

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