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SystemVerilog for verification : a guide to learning the testbench language features

By: Spear, Chris.
Contributor(s): Tumbush, Greg.
Material type: materialTypeLabelBookPublisher: New York : Springer, ©2012Edition: 3rd ed.Description: xliii, 464 p. : ill. ; 24 cm.ISBN: 9781489995001.Subject(s): SystemVerilog (Computer hardware description language) | Integrated circuits -- Verification
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Reference Reference IIITD
Electronics and Communication Engineering REF 621.392 SPE-S (Browse shelf) Checked out Not For Loan 17/08/2020 010125

Verification and High-Level Synthesis of VLSI Designs Winter

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Includes bibliographical references and index.

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