Completion Detection in Asynchronous Circuits (Record no. 174529)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03437nam a22005295i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-031-18397-3 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240423125126.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 221108s2022 sz | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9783031183973 |
| -- | 978-3-031-18397-3 |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1007/978-3-031-18397-3 |
| Source of number or code | doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7867-7867.5 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TJFC |
| Source | bicssc |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TEC008010 |
| Source | bisacsh |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TJFC |
| Source | thema |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3815 |
| Edition number | 23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Srivastava, Pallavi. |
| Relator term | author. |
| Relator code | aut |
| -- | http://id.loc.gov/vocabulary/relators/aut |
| 245 10 - TITLE STATEMENT | |
| Title | Completion Detection in Asynchronous Circuits |
| Medium | [electronic resource] : |
| Remainder of title | Toward Solution of Clock-Related Design Challenges / |
| Statement of responsibility, etc | by Pallavi Srivastava. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2022. |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2022. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | XV, 119 p. 65 illus., 51 illus. in color. |
| Other physical details | online resource. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Introduction to asynchronous circuit design -- "Preliminary considerations for asynchronous circuit design." -- "Completion detection schemes for asynchronous design style" -- Case Studies: Barrel shifter and binary adders -- "Generic Architecture of deterministic completion detection scheme" -- Architecture optimization using deterministic completion detection" -- Simulations. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits. Analyzes circuit design techniques in the context of timing constraints; Develops a generic, deterministic completion detection scheme for asynchronous circuits using bundled data protocol; Demonstrates a single-precision, asynchronous bundled data barrel shifter to validate the completion detection scheme. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Electronic circuit design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer architecture. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Electronic Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Electronics Design and Verification. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Processor Architectures. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY | |
| Title | Springer Nature eBook |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Printed edition: |
| International Standard Book Number | 9783031183966 |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Printed edition: |
| International Standard Book Number | 9783031183980 |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Printed edition: |
| International Standard Book Number | 9783031183997 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://doi.org/10.1007/978-3-031-18397-3">https://doi.org/10.1007/978-3-031-18397-3</a> |
| 912 ## - | |
| -- | ZDB-2-SCS |
| 912 ## - | |
| -- | ZDB-2-SXCS |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks-CSE-Springer |
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