000			00978nam a22003137a 4500
003			IIITD
005			20250813170701.0
008			250731b |||||||| |||| 00| 0 eng d
020			_a9780983497301
040			_aIIITD
082			_a621.39 _bREA-V
100			_aReadler, Blaine C.
245			_aVerilog by example : _ba concise introduction for FPGA design _cby Blaine C. Readler
260			_aNorth Carolina : _bFull Arc Press, _c©2011
300			_a114 p. : _bill. ; _c24 cm.
504			_aIncludes bibliographical references and index.
505			_t1. The Tool Flow
505			_t2. In and Out
505			_t3. Clocks and Registers
505			_t4. State Machines
505			_t5. Modular Design
505			_t6. Memories
505			_t7. Managing Clocks
505			_t8. I/O Flavors
505			_t9. A Taste of Simulation
650			_aField programmable gate arrays
650			_aVerilog (Computer hardware description language)
942			_2ddc _cBK
999			_c209244 _d209244