000			01215nam a22003737a 4500
003			IIITD
005			20250215125307.0
008			250212b |||||||| |||| 00| 0 eng d
020			_a9789390727490
040			_aIIITD
082			_a004.22 _bSAR-A
100			_aSarangi, Smruti Ranjan
245			_aAdvanced computer architecture _cby Smruti Ranjan Sarangi
260			_aChennai : _bMcGraw Hill, _c©2021
300			_axviii, 688 p. : _bill. ; _c24 cm.
500			_aInclude Index
505			_t1.Introduction
505			_t2. Out-of-order pipelines
505			_t3. The fetch and decode stages
505			_t4. The issue, execute and commit stages
505			_t5. Alternative approaches to issue and commit
505			_t6. Graphics processors
505			_t7. Caches
505			_t8. On-chip network
505			_t9. Multicore systems: coherence, consistency and transactional memory
505			_t10. Main memory
505			_t11. Power and temperature
505			_t12. Reliability
505			_t13. Secure processor architectures
505			_t14. Architectures for machine learning
650			_aComputer organization
650			_aComputer architecture
942			_cBK _2ddc
999			_c189867 _d189867