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020 _a9783540715283
_9978-3-540-71528-3
024 7 _a10.1007/978-3-540-71528-3
_2doi
050 4 _aQA75.5-76.95
072 7 _aUYA
_2bicssc
072 7 _aCOM014000
_2bisacsh
072 7 _aUYA
_2thema
082 0 4 _a004.0151
_223
245 1 0 _aTransactions on High-Performance Embedded Architectures and Compilers I
_h[electronic resource] /
_cedited by Mike O'Boyle, Francois Bodin, Marcelo Cintra, Sally A. McKee.
250 _a1st ed. 2007.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg :
_bImprint: Springer,
_c2007.
300 _aXVI, 368 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aTransactions on High-Performance Embedded Architectures and Compilers,
_x1864-3078 ;
_v4050
505 0 _aHigh Performance Processor Chips -- High Performance Processor Chips -- High-Performance Embedded Architecture and Compilation Roadmap -- 1: First International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2005. Best Papers -- to Part 1 -- Quick and Practical Run-Time Evaluation of Multiple Program Optimizations -- Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems -- GCH: Hints for Triggering Garbage Collections -- Memory-Centric Security Architecture -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- 2: Optimizing Compilers -- to Part 2 -- Convergent Compilation Applied to Loop Unrolling -- Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations -- Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures -- Automatic Discovery of Coarse-Grained Parallelism in Media Applications -- An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors -- 3: ACM International Conference on Computing Frontiers 2006. Best Papers -- to Part 3 -- Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology -- Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture -- Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors -- Selective Code Compression Scheme for Embedded Systems -- A Prefetching Algorithm for Multi-speed Disks -- Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation.
650 0 _aComputer science.
650 0 _aComputer arithmetic and logic units.
650 0 _aMicroprocessors.
650 0 _aComputer architecture.
650 0 _aComputer input-output equipment.
650 0 _aLogic design.
650 0 _aComputer networks .
650 1 4 _aTheory of Computation.
650 2 4 _aArithmetic and Logic Structures.
650 2 4 _aProcessor Architectures.
650 2 4 _aInput/Output and Data Communications.
650 2 4 _aLogic Design.
650 2 4 _aComputer Communication Networks.
700 1 _aO'Boyle, Mike.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aBodin, Francois.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aCintra, Marcelo.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aMcKee, Sally A.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
710 2 _aSpringerLink (Online service)
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783540715276
776 0 8 _iPrinted edition:
_z9783540836759
830 0 _aTransactions on High-Performance Embedded Architectures and Compilers,
_x1864-3078 ;
_v4050
856 4 0 _uhttps://doi.org/10.1007/978-3-540-71528-3
912 _aZDB-2-SCS
912 _aZDB-2-SXCS
912 _aZDB-2-LNC
942 _cSPRINGER
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