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020 _a9783642368127
_9978-3-642-36812-7
024 7 _a10.1007/978-3-642-36812-7
_2doi
050 4 _aTK7885-7895
072 7 _aUK
_2bicssc
072 7 _aCOM067000
_2bisacsh
072 7 _aUK
_2thema
082 0 4 _a004
_223
245 1 0 _aReconfigurable Computing: Architectures, Tools and Applications
_h[electronic resource] :
_b9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013, Proceedings /
_cedited by Philip Brisk, José Gabriel de Figueiredo Coutinho, Pedro Diniz.
250 _a1st ed. 2013.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg :
_bImprint: Springer,
_c2013.
300 _aXVI, 238 p. 104 illus.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aTheoretical Computer Science and General Issues,
_x2512-2029 ;
_v7806
505 0 _aHeterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications -- Hardware Acceleration of Genetic Sequence Alignment -- An FPGA Acceleration for the Kd-tree Search in Photon Mapping -- SEU Resilience of DES, AES in SRAM-based FPGA -- An Architecture for IPv6 Lookup Using Parallel Index Generation Units -- Hardware Index to Set Partition Converter -- Teaching SoC Using Video Games to Improve Student Engagement -- Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-based Custom Computing -- Hardware Acceleration of Matrix Multiplication Over Small Prime Finite Fields -- Flexible Design of a Modular Simultaneous Exponentiation Core for Embedded Platforms -- Architecture for Transparent Binary Acceleration of Loops with Memory Accesses -- Parametric Optimization of Reconfigurable Designs using Machine Learning -- Fast Template-based Heterogeneous MPSoC Synthesis on FPGA -- Hierarchical and Multiple Switching NoC with Floorplan based Adaptability -- Performance Analysis And Optimization of High Density Tree-Based 3D Multilevel FPGA.
520 _aThis book constitutes the thoroughly refereed conference proceedings of the 9th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2013, held in Los Angeles, CA, USA, in March 2013. The 28 revised papers presented, consisting of 20 full papers and 11 poster papers were carefully selected from 41 submissions. The topics covered are applications, arithmetic, design optimization for FPGAs, architectures, place and routing.
650 0 _aComputers.
650 0 _aComputer engineering.
650 0 _aComputer networks .
650 0 _aAlgorithms.
650 1 4 _aComputer Hardware.
650 2 4 _aComputer Engineering and Networks.
650 2 4 _aAlgorithms.
700 1 _aBrisk, Philip.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _ade Figueiredo Coutinho, José Gabriel.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aDiniz, Pedro.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
710 2 _aSpringerLink (Online service)
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783642368110
776 0 8 _iPrinted edition:
_z9783642368134
830 0 _aTheoretical Computer Science and General Issues,
_x2512-2029 ;
_v7806
856 4 0 _uhttps://doi.org/10.1007/978-3-642-36812-7
912 _aZDB-2-SCS
912 _aZDB-2-SXCS
912 _aZDB-2-LNC
942 _cSPRINGER
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