000 | 04110nam a22005535i 4500 | ||
---|---|---|---|
001 | 978-981-19-8551-5 | ||
003 | DE-He213 | ||
005 | 20240423125321.0 | ||
007 | cr nn 008mamaa | ||
008 | 230301s2023 si | s |||| 0|eng d | ||
020 |
_a9789811985515 _9978-981-19-8551-5 |
||
024 | 7 |
_a10.1007/978-981-19-8551-5 _2doi |
|
050 | 4 | _aTK7885-7895 | |
050 | 4 | _aTA169-169.3 | |
072 | 7 |
_aUK _2bicssc |
|
072 | 7 |
_aCOM067000 _2bisacsh |
|
072 | 7 |
_aUK _2thema |
|
082 | 0 | 4 |
_a004.24 _223 |
100 | 1 |
_aLi, Xiaowei. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut |
|
245 | 1 | 0 |
_aBuilt-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design _h[electronic resource] : _bA Self-Test, Self-Diagnosis, and Self-Repair-Based Approach / _cby Xiaowei Li, Guihai Yan, Cheng Liu. |
250 | _a1st ed. 2023. | ||
264 | 1 |
_aSingapore : _bSpringer Nature Singapore : _bImprint: Springer, _c2023. |
|
300 |
_aXVIII, 304 p. 1 illus. _bonline resource. |
||
336 |
_atext _btxt _2rdacontent |
||
337 |
_acomputer _bc _2rdamedia |
||
338 |
_aonline resource _bcr _2rdacarrier |
||
347 |
_atext file _bPDF _2rda |
||
505 | 0 | _aChapter 1: Introduction -- Chapter 2: Fault-tolerant general circuits with 3S -- Chapter 3: Fault-tolerant general purposed processors with 3S -- Chapter 4: Fault-tolerant network-on-chip with 3S -- Chapter 5: Fault-tolerant deep learning processors with 3S -- Chapter 6: Conclusion. | |
520 | _aWith the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or “3S” for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not onlyoffers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs. . | ||
650 | 0 | _aComputers. | |
650 | 0 | _aMicroprocessors. | |
650 | 0 | _aComputer architecture. | |
650 | 1 | 4 | _aHardware Performance and Reliability. |
650 | 2 | 4 | _aComputer Hardware. |
650 | 2 | 4 | _aProcessor Architectures. |
700 | 1 |
_aYan, Guihai. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut |
|
700 | 1 |
_aLiu, Cheng. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut |
|
710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer Nature eBook | |
776 | 0 | 8 |
_iPrinted edition: _z9789811985508 |
776 | 0 | 8 |
_iPrinted edition: _z9789811985522 |
776 | 0 | 8 |
_iPrinted edition: _z9789811985539 |
856 | 4 | 0 | _uhttps://doi.org/10.1007/978-981-19-8551-5 |
912 | _aZDB-2-SCS | ||
912 | _aZDB-2-SXCS | ||
942 | _cSPRINGER | ||
999 |
_c176636 _d176636 |