Course reserves for Verification and High-Level Synthesis of VLSI Designs
- Term: WNT
- Department: ECE
- Course number: ECE5xx
- Instructors:
- Dr. Sumit Mediratta
| Title | Author | Item type | Location | Collection | Call number | Copy number | Status | Date due | Notes | Link |
|---|---|---|---|---|---|---|---|---|---|---|
| System verilog assertions and functional coverage : | Mehta, Ashok B. | Reference | IIITD Reference |
Computer Science and Engineering | REF 621.392 MEH-S | Checked out Not for loan | 22/05/2024 | |||
| SystemVerilog for verification : | Spear, Chris | Reference | IIITD Reference |
Electronics and Communication Engineering | REF 621.392 SPE-S | Checked out Not for loan | 22/05/2024 | |||
| System design with system C | Reference | IIITD Reference |
Computer Science and Engineering | REF 004.21 GRO-S | Not for loan |