MARC details
| 000 -LEADER |
|---|
| fixed length control field |
03633cam a22003618a 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
16453917 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
IIITD |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20140925151240.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
100910s2011 flu b 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2010036073 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781439837108 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
DLC |
| Transcribing agency |
DLC |
| 042 ## - AUTHENTICATION CODE |
|---|
| Authentication code |
pcc |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK5105.546 |
| Item number |
.D476 2011 |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.3815 |
| Edition number |
22 |
| Item number |
FLI-D |
| 084 ## - OTHER CLASSIFICATION NUMBER |
|---|
| Classification number |
COM011000 |
| -- |
COM059000 |
| Source of number |
bisacsh |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Flich, Jose. |
| 245 00 - TITLE STATEMENT |
|---|
| Title |
Designing network on-chip architectures in the nanoscale era |
| Statement of responsibility, etc |
Jose Flich, Davide Bertozzi. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc |
Boca Raton, FL : |
| Name of publisher, distributor, etc |
Chapman & Hall/CRC, |
| Date of publication, distribution, etc |
2011. |
| 263 ## - PROJECTED PUBLICATION DATE |
|---|
| Projected publication date |
1012 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxxviii 490p. |
| 490 0# - SERIES STATEMENT |
|---|
| Series statement |
Chapman & Hall/CRC computational science |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references and index. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
"Paving the way for the use of network on-chip architectures in 2015 platforms, this book presents the industrial requirements for such long-term platforms as well as the main research findings for technology-aware architecture design. It covers homogeneous design techniques and guidelines, including the solutions that are most appealing to the industry and best suited to meet the requirements of on-chip integration. Each chapter deals with a specific key architecture design, including fault tolerant design, topology selection, dynamic voltage and frequency scaling, synchronization, network on-chip resources exposed to the architecture, routing algorithms, and collective communication"-- |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
"Chip Multiprocessors (CMPs) are diving very aggressively into the marketplace since past efforts to speed up processor architectures in ways that do not modify the basic von Neumann computing model have encountered hard limits. The power consumption of the chip becomes the limiting factor and sets the rules for future CMP systems. As a result, the microprocessor industry is today leading the development of multicore and many-core architectures where, as the number of cores increases, efficient communication among them and with off-chip resources becomes key to achieve the intended performance scalability. This trend has helped overcome the skepticism of some system architects to embrace on-chip interconnection networks as a key enabler for effective system integration. Networks-on-chip (NoCs) make performance scalability more a matter of instantiation and connectivity rather than increasing complexity of specific architecture building blocks. This book comes as a timely and welcome addition to the wide spectrum of available NoC literature, as it has been designed with the purpose of describing in a coherent and well-grounded fashion the foundation of NoC technology, above and beyond a simple overview of research ideas and/or design experiences. It covers in depth architectural and implementation concepts and gives clear guidelines on how to design the key network component, providing strong guidance in a research field that is starting to stabilize, bringing "sense and simplicity" and teaching hard lessons from the design trenches. The book also covers upcoming research and development trends, such as vertical integration and variation tolerant design. It is a much needed "how-to" guide and an ideal stepping stone for the next ten years of NoC evolution"-- |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Networks on a chip. |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
COMPUTERS / Systems Architecture / General |
| Source of heading or term |
bisacsh. |
| 650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
COMPUTERS / Computer Engineering |
| Source of heading or term |
bisacsh. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Bertozzi, Davide. |
| 906 ## - LOCAL DATA ELEMENT F, LDF (RLIN) |
|---|
| a |
7 |
| b |
cbc |
| c |
orignew |
| d |
1 |
| e |
ecip |
| f |
20 |
| g |
y-gencatlg |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Books |
