MARC details
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02821cam a22003612 b4500 |
| 001 - CONTROL NUMBER |
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8565980 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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20230921020002.0 |
| 006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS--GENERAL INFORMATION |
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m d |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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cr n |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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030328e20031105njua s|||||||| 2|eng|d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9780471441489 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| Terms of availability |
9788126519316 |
| 024 3# - OTHER STANDARD IDENTIFIER |
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| Standard number or code |
9780471441489 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(WaSeSS)ssj0000293726 |
| 037 ## - SOURCE OF ACQUISITION |
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| Source of stock number/acquisition |
00028608 |
| 040 ## - CATALOGING SOURCE |
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| Original cataloging agency |
BIP US |
| Modifying agency |
WaSeSS |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
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| Classification number |
TK7885.7 |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.392 |
| Edition number |
22 |
| Item number |
PAD-D |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Padmanabhan, T. R. |
| Relator term |
Author |
| 210 10 - ABBREVIATED TITLE |
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| Abbreviated title |
Design Through Verilog HDL |
| 245 10 - TITLE STATEMENT |
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| Title |
Design through verilog HDL |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
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| Date of publication, distribution, etc |
2003. |
| Place of publication, distribution, etc |
New Delhi : |
| Name of publisher, distributor, etc |
Wiley, |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xii, 455 p. |
| 506 ## - RESTRICTIONS ON ACCESS NOTE |
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| Terms governing access |
License restrictions may limit access. |
| 520 8# - SUMMARY, ETC. |
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| Summary, etc |
Annotation |
| Expansion of summary note |
A comprehensive resource on Verilog HDL for beginners and expertsLarge and complicated digital circuits can be incorporated into hardware by using Verilog, a hardware description language (HDL). A designer aspiring to master this versatile language must first become familiar with its constructs, practice their use in real applications, and apply them in combinations in order to be successful. Design Through Verilog HDL affords novices the opportunity to perform all of these tasks, while also offering seasoned professionals a comprehensive resource on this dynamic tool.Describing a design using Verilog is only half the story: writing test-benches, testing a design for all its desired functions, and how identifying and removing the faults remain significant challenges. Design Through Verilog HDL addresses each of these issues concisely and effectively. The authors discuss constructs through illustrative examples that are tested with popular simulation packages, ensuring the subject matter remains practically relevant.Other important topics covered include:PrimitivesGate and Net delaysBuffersCMOS switchesState machine designFurther, the authors focus on illuminating the differences between gate level, data flow, and behavioral styles of Verilog, a critical distinction for designers. The book's final chapters deal with advanced topics such as timescales, parameters and related constructs, queues, and switch level design.Each chapter concludes with exercises that both ensure readers have mastered the present material and stimulate readers to explore avenues of their own choosing. Written and assembled in a paced, logical manner, Design Through Verilog HDL provides professionals, graduate students, and advanced undergraduates with a one-of-a-kind resource. |
| 521 ## - TARGET AUDIENCE NOTE |
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| Target audience note |
Scholarly & Professional |
| Source |
John Wiley & Sons, Incorporated |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
System design |
| 658 ## - INDEX TERM--CURRICULUM OBJECTIVE |
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| Main curriculum objective |
Verilog |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Sundari, B. Bala Tripura |
| Relator term |
Author |
| 773 #0 - HOST ITEM ENTRY |
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| Title |
IEEE-Wiley eBooks Library |
| 910 ## - USER-OPTION DATA (OCLC) |
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| User-option data |
Bowker Global Books in Print record |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Item type |
Books |
| Koha issues (borrowed), all copies |
6 |
