Transactions on High-Performance Embedded Architectures and Compilers IV (Record no. 185652)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 05502nam a22006255i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-642-24568-8 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240423130144.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 111114s2011 gw | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9783642245688 |
| -- | 978-3-642-24568-8 |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1007/978-3-642-24568-8 |
| Source of number or code | doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | QA76.9.C62 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | UK |
| Source | bicssc |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | COM036000 |
| Source | bisacsh |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | UK |
| Source | thema |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 004.01513 |
| Edition number | 23 |
| 245 10 - TITLE STATEMENT | |
| Title | Transactions on High-Performance Embedded Architectures and Compilers IV |
| Medium | [electronic resource] / |
| Statement of responsibility, etc | edited by Per Stenström. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2011. |
| 264 #1 - | |
| -- | Berlin, Heidelberg : |
| -- | Springer Berlin Heidelberg : |
| -- | Imprint: Springer, |
| -- | 2011. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | XV, 430 p. 222 illus. |
| Other physical details | online resource. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 490 1# - SERIES STATEMENT | |
| Series statement | Transactions on High-Performance Embedded Architectures and Compilers, |
| International Standard Serial Number | 1864-3078 ; |
| Volume number/sequential designation | 6760 |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors -- Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces -- Compiler Directed Issue Queue Energy Reduction -- A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors -- Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors -- Special Section on High-Performance and Embedded Architectures and Compilers (HiPEAC) -- A Highly Scalable Parallel Implementation of H.264 -- Communication Based Proactive Link Power Management -- Finding Extreme Behaviors in Microprocessor Workloads -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Special Section on Selected papers from the Workshop on Software and Hardware Challenges of Many-core Platforms -- Transaction Reordering to Reduce Aborts in Software Transactional Memory -- A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture -- A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM -- Software Transactional Memory Validation – Time and Space Considerations Tiled Multi-Core Stream Architecture -- An Efficient and Flexible Task Management for Many Cores -- Special Section on International Symposium on Systems, ArchitecturesModeling and Simulation -- On Two-layer Brain-inspired Hierarchical Topologies: A Rent’s Rule Approach -- Advanced Packet Segmentation and Buffering Algorithms in Network Processors -- Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation -- A Cost Model for Partial Dynamic Reconfiguration -- Heterogeneous Design in Functional DIF -- Signature-based Calibration of Analytical Performance Models for System-level Design Space Exploration. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This 4th issue contains 21 papers carefully reviewed and selected out of numerous submissions and is divided in four sections. The first section contains five regular papers. The second section consists of the top four papers from the 4th International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The third section contains a set of six papers providing a snap-shot from the Workshop on Software and Hardware Challenges of Manycore Platforms, SHCMP 2008 held in Beijing, China, in June 2008. The fourth section consists of six papers from the 8th IEEE International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS VIII (2008) held in Samos, Greece, in July 2008. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer arithmetic and logic units. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer architecture. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer input-output equipment. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Logic design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer networks . |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Compilers (Computer programs). |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Arithmetic and Logic Structures. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Processor Architectures. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Input/Output and Data Communications. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Logic Design. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer Communication Networks. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Compilers and Interpreters. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Stenström, Per. |
| Relator term | editor. |
| Relator code | edt |
| -- | http://id.loc.gov/vocabulary/relators/edt |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY | |
| Title | Springer Nature eBook |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Printed edition: |
| International Standard Book Number | 9783642245671 |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Printed edition: |
| International Standard Book Number | 9783642245695 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| Uniform title | Transactions on High-Performance Embedded Architectures and Compilers, |
| -- | 1864-3078 ; |
| Volume number/sequential designation | 6760 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | <a href="https://doi.org/10.1007/978-3-642-24568-8">https://doi.org/10.1007/978-3-642-24568-8</a> |
| 912 ## - | |
| -- | ZDB-2-SCS |
| 912 ## - | |
| -- | ZDB-2-SXCS |
| 912 ## - | |
| -- | ZDB-2-LNC |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks-CSE-Springer |
No items available.