Cryptographic Hardware and Embedded Systems - CHES 2007 (Record no. 179516)

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001 - CONTROL NUMBER
control field 978-3-540-74735-2
003 - CONTROL NUMBER IDENTIFIER
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005 - DATE AND TIME OF LATEST TRANSACTION
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007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
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008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 100301s2007 gw | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9783540747352
-- 978-3-540-74735-2
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/978-3-540-74735-2
Source of number or code doi
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number QA268
072 #7 - SUBJECT CATEGORY CODE
Subject category code GPJ
Source bicssc
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Subject category code URY
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Subject category code COM083000
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Subject category code GPJ
Source thema
072 #7 - SUBJECT CATEGORY CODE
Subject category code URY
Source thema
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 005.824
Edition number 23
245 10 - TITLE STATEMENT
Title Cryptographic Hardware and Embedded Systems - CHES 2007
Medium [electronic resource] :
Remainder of title 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings /
Statement of responsibility, etc edited by Pascal Paillier, Ingrid Verbauwhede.
250 ## - EDITION STATEMENT
Edition statement 1st ed. 2007.
264 #1 -
-- Berlin, Heidelberg :
-- Springer Berlin Heidelberg :
-- Imprint: Springer,
-- 2007.
300 ## - PHYSICAL DESCRIPTION
Extent XIV, 468 p.
Other physical details online resource.
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-- txt
-- rdacontent
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-- computer
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-- rdamedia
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-- online resource
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-- text file
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490 1# - SERIES STATEMENT
Series statement Security and Cryptology,
International Standard Serial Number 2946-1863 ;
Volume number/sequential designation 4727
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Differential and Higher Order Attacks -- A First-Order DPA Attack Against AES in Counter Mode with Unknown Initial Counter -- Gaussian Mixture Models for Higher-Order Side Channel Analysis -- Side Channel Cryptanalysis of a Higher Order Masking Scheme -- Random Number Generation and Device Identification -- High-Speed True Random Number Generation with Logic Gates Only -- FPGA Intrinsic PUFs and Their Use for IP Protection -- Logic Styles: Masking and Routing -- Evaluation of the Masked Logic Style MDPL on a Prototype Chip -- Masking and Dual-Rail Logic Don’t Add Up -- DPA-Resistance Without Routing Constraints? -- Efficient Algorithms for Embedded Processors -- On the Power of Bitslice Implementation on Intel Core2 Processor -- Highly Regular Right-to-Left Algorithms for Scalar Multiplication -- MAME: A Compression Function with Reduced Hardware Requirements -- Collision Attacks and Fault Analysis -- Collision Attacks on AES-Based MAC: Alpha-MAC -- Secret External Encodings Do Not Prevent Transient Fault Analysis -- Two New Techniques of Side-Channel Cryptanalysis -- High Speed AES Implementations -- AES Encryption Implementation and Analysis on Commodity Graphics Processing Units -- Multi-gigabit GCM-AES Architecture Optimized for FPGAs -- Public-Key Cryptography -- Arithmetic Operators for Pairing-Based Cryptography -- FPGA Design of Self-certified Signature Verification on Koblitz Curves -- How to Maximize the Potential of FPGA Resources for Modular Exponentiation -- Implementation Cost of Countermeasures -- TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks -- Power Analysis Resistant AES Implementation with Instruction Set Extensions -- Security Issues for RF and RFID -- Power and EM Attacks on Passive RFID Devices -- RFID Noisy Reader How toPrevent from Eavesdropping on the Communication? -- RF-DNA: Radio-Frequency Certificates of Authenticity -- Special Purpose Hardware for Cryptanalysis -- CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method -- Collision Search for Elliptic Curve Discrete Logarithm over GF(2 m ) with FPGA -- A Hardware-Assisted Realtime Attack on A5/2 Without Precomputations -- Side Channel Analysis -- Differential Behavioral Analysis -- Information Theoretic Evaluation of Side-Channel Resistant Logic Styles -- Problems and Solutions for Lightweight Devices -- On the Implementation of a Fast Prime Generation Algorithm -- PRESENT: An Ultra-Lightweight Block Cipher -- Cryptographic Hardware and Embedded Systems - CHES 2007.
520 ## - SUMMARY, ETC.
Summary, etc CHES2007,theninthworkshoponCryptographicHardwareandEmbeddedS- tems, was sponsored by the International Association for Cryptologic Research (IACR) and held in Vienna, Austria, September 10–13, 2007. The workshop - ceived 99 submissions from 24 countries, of which the Program Committee (39 members from 15 countries) selected 31 for presentation. For the ?rst time in the history of CHES, each submission was reviewed by at least four reviewers instead of three (and at least ?ve for submissions by PC members, those now being limited to two per member) and many submitted papers have received plenty of extra reviews (some papers received up to nine reviews), thus totalling the unprecedented record of 483 reviews overall. Thepaperscollectedinthisvolumerepresentcutting-edgeworldwideresearch in the rapidly evolving ?elds of crypto-hardware, fault-based and side-channel cryptanalysis, and embedded cryptography, at the crossing of academic and - dustrial research. The wide diversity of subjects appearing in these proceedings covers virtually all related areas and shows our e?orts to extend the scope of CHES more than usual. Although a relatively young workshop, CHES is now ?rmlyestablishedasascienti?ceventofreferenceappreciatedbymoreandmore renowned experts of theory and practice: many high-quality works were subm- ted, all of which, sadly, could not be accepted. Selecting from so many good worksis no easy task and our deepest thanks go to the members of the Program Committee for their involvement, excellence, and team spirit. We are grateful to the numerous external reviewers listed below for their expertise and assistance in our deliberations.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Cryptography.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Data encryption (Computer science).
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer networks .
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computers, Special purpose.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Logic design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Operating systems (Computers).
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Electronic data processing
General subdivision Management.
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Cryptology.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer Communication Networks.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Special Purpose and Application-Based Systems.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Logic Design.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Operating Systems.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element IT Operations.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Paillier, Pascal.
Relator term editor.
Relator code edt
-- http://id.loc.gov/vocabulary/relators/edt
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Verbauwhede, Ingrid.
Relator term editor.
Relator code edt
-- http://id.loc.gov/vocabulary/relators/edt
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer Nature eBook
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9783540747345
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9783540843399
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Security and Cryptology,
-- 2946-1863 ;
Volume number/sequential designation 4727
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="https://doi.org/10.1007/978-3-540-74735-2">https://doi.org/10.1007/978-3-540-74735-2</a>
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942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type eBooks-CSE-Springer

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