Transactions on High-Performance Embedded Architectures and Compilers I
Transactions on High-Performance Embedded Architectures and Compilers I [electronic resource] /
edited by Mike O'Boyle, Francois Bodin, Marcelo Cintra, Sally A. McKee.
- 1st ed. 2007.
- XVI, 368 p. online resource.
- Transactions on High-Performance Embedded Architectures and Compilers, 4050 1864-3078 ; .
- Transactions on High-Performance Embedded Architectures and Compilers, 4050 .
High Performance Processor Chips -- High Performance Processor Chips -- High-Performance Embedded Architecture and Compilation Roadmap -- 1: First International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2005. Best Papers -- to Part 1 -- Quick and Practical Run-Time Evaluation of Multiple Program Optimizations -- Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems -- GCH: Hints for Triggering Garbage Collections -- Memory-Centric Security Architecture -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- 2: Optimizing Compilers -- to Part 2 -- Convergent Compilation Applied to Loop Unrolling -- Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations -- Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures -- Automatic Discovery of Coarse-Grained Parallelism in Media Applications -- An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors -- 3: ACM International Conference on Computing Frontiers 2006. Best Papers -- to Part 3 -- Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology -- Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture -- Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors -- Selective Code Compression Scheme for Embedded Systems -- A Prefetching Algorithm for Multi-speed Disks -- Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation.
9783540715283
10.1007/978-3-540-71528-3 doi
Computer science.
Computer arithmetic and logic units.
Microprocessors.
Computer architecture.
Computer input-output equipment.
Logic design.
Computer networks .
Theory of Computation.
Arithmetic and Logic Structures.
Processor Architectures.
Input/Output and Data Communications.
Logic Design.
Computer Communication Networks.
QA75.5-76.95
004.0151
High Performance Processor Chips -- High Performance Processor Chips -- High-Performance Embedded Architecture and Compilation Roadmap -- 1: First International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2005. Best Papers -- to Part 1 -- Quick and Practical Run-Time Evaluation of Multiple Program Optimizations -- Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems -- GCH: Hints for Triggering Garbage Collections -- Memory-Centric Security Architecture -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- 2: Optimizing Compilers -- to Part 2 -- Convergent Compilation Applied to Loop Unrolling -- Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations -- Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures -- Automatic Discovery of Coarse-Grained Parallelism in Media Applications -- An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors -- 3: ACM International Conference on Computing Frontiers 2006. Best Papers -- to Part 3 -- Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology -- Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture -- Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors -- Selective Code Compression Scheme for Embedded Systems -- A Prefetching Algorithm for Multi-speed Disks -- Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation.
9783540715283
10.1007/978-3-540-71528-3 doi
Computer science.
Computer arithmetic and logic units.
Microprocessors.
Computer architecture.
Computer input-output equipment.
Logic design.
Computer networks .
Theory of Computation.
Arithmetic and Logic Structures.
Processor Architectures.
Input/Output and Data Communications.
Logic Design.
Computer Communication Networks.
QA75.5-76.95
004.0151