000 01276cam a2200313 a 4500
001 14169035
005 20171028020003.0
008 051115s2006 nyua b 001 0 eng
010 _a 2005937330
020 _a9788181284839
040 _aDLC
_cDLC
_dDLC
050 0 0 _aTK7874.75
_b.H33 2006
082 0 0 _a621.395
_222
_bHAC-L
100 1 _aHachtel, Gary D.
245 1 0 _aLogic synthesis and verification algorithms
_cGary Hachtel, Fabio Somenzi.
260 _aNew York :
_bSpringer,
_cc2006.
300 _axxxii, 564 p. :
_bill. ;
_c26 cm.
504 _aIncludes bibliographical references (p. 537-553) and index.
650 0 _aIntegrated circuits
_xVery large scale integration
_xDesign
_xData processing.
650 0 _aLogic design
_xData processing.
650 0 _aIntegrated circuits
_xVerification.
650 0 _aComputer-aided design.
700 1 _aSomenzi, Fabio.
856 4 2 _3Publisher description
_uhttp://www.loc.gov/catdir/enhancements/fy0663/2005937330-d.html
856 4 1 _3Table of contents only
_uhttp://www.loc.gov/catdir/enhancements/fy0824/2005937330-t.html
906 _a7
_bcbc
_corignew
_d2
_eepcn
_f20
_gy-gencatlg
942 _2ddc
_cBK
_01
999 _c8329
_d8329