000 01791cam a22004217a 4500
001 14155693
005 20190129020002.0
008 051027s2005 nyua b 001 0 eng d
010 _a 2005936398
015 _aGBA551511
_2bnb
016 7 _a013213996
_2Uk
020 _a9788181288899
035 _a(OCoLC)ocm57593669
040 _aEUN
_cEUN
_dOCLCQ
_dOHX
_dUKM
_dOCL
_dFDA
_dBAKER
_dNDD
_dCOD
_dDLC
042 _alccopycat
050 0 0 _aTK7872.F73
_bS58 2005
072 7 _aTK
_2lcco
082 0 0 _a621.397
_222
_bSHU-C
100 1 _aShu, Keliu.
245 1 0 _aCMOS PLL synthesizers :
_banalysis and design
_cKeliu Shu, Edgar Sánchez-Sinencio.
246 3 _aCMOS phase-locked loop synthesizers
260 _aNew Delhi. :
_bSpringer,
_cc2005.
300 _axvi, 215 p. :
_bill. ;
_c25 cm.
490 0 _aKluwer international series in engineering and computer science ;
_v783.
_aAnalog circuits and signal processing
504 _aIncludes bibliographical references and index.
650 0 _aMetal oxide semiconductors, Complementary.
650 0 _aPhase-locked loops.
650 0 _aFrequency synthesizers
_xDesign and construction.
700 1 _aSánchez-Sinencio, Edgar.
830 0 _aKluwer international series in engineering and computer science ;
_v783.
830 0 _aKluwer international series in engineering and computer science.
_pAnalog circuits and signal processing.
856 4 1 _3Table of contents only
_uhttp://www.loc.gov/catdir/toc/fy0608/2005936398.html
856 4 2 _3Publisher description
_uhttp://www.loc.gov/catdir/enhancements/fy0663/2005936398-d.html
906 _a7
_bcbc
_ccopycat
_d2
_encip
_f20
_gy-gencatlg
942 _2ddc
_cBK
_03
999 _c8263
_d8263