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| 003 | IIITD | ||
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| 040 | _aa | ||
| 082 |
_a621.392 _bBHA-V |
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| 100 | _aBhasker, J. | ||
| 245 |
_aVerilog HDL synthesis : _ba practical primer _cJ. Bhasker. |
||
| 260 |
_bBSP, _c©2008. _aNew Delhi: |
||
| 300 | _a216 p. | ||
| 600 | _aLogic design--Data processing | ||
| 610 | _aVerilog (Computer hardware description language) | ||
| 942 |
_2ddc _cBK _057 |
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| 999 |
_c6986 _d6986 |
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