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008			121227s2000 gw | s |||| 0|eng d
020			_a9783540453734 _9978-3-540-45373-4
024	7		_a10.1007/3-540-45373-3 _2doi
050		4	_aQA76.9.S88
072		7	_aUYD _2bicssc
072		7	_aCOM011000 _2bisacsh
072		7	_aUYD _2thema
082	0	4	_a004.2 _223
245	1	0	_aIntegrated Circuit Design: Power and Timing Modeling, Optimization and Simulation _h[electronic resource] : _b10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000 Proceedings / _cedited by Dimitrios Soudris, Peter Pirsch, Erich Barke.
250			_a1st ed. 2000.
264		1	_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg : _bImprint: Springer, _c2000.
300			_aXII, 338 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aLecture Notes in Computer Science, _x1611-3349 ; _v1918
505	0		_aOpening -- Constraints, Hurdles and Opportunities for a Successful European Take-Up Action -- RTL Power Modeling -- Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques -- Power Models for Semi-autonomous RTL Macros -- Power Macro-Modelling for Firm-Macro -- RTL Estimation of Steering Logic Power -- Power Estimation and Optimization -- Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers -- Framework for High-Level Power Estimation of Signal Processing Architectures -- Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses -- Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions -- System-Level Design -- A Holistic Approach to System Level Energy Optimization -- Early Power Estimation for System-on-Chip Designs -- Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures -- Transistor-Level Modeling -- Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design -- Impact of Voltage Scaling on Glitch Power Consumption -- Degradation Delay Model Extension to CMOS Gates -- Second Generation Delay Model for Submicron CMOS Process -- Asynchronous Circuit Design -- Semi-modular Latch Chains for Asynchronous Circuit Design -- Asynchronous First-in First-out Queues -- Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance -- VLSI Implementation of a Low-Power High-Speed Self-Timed Adder -- Power Efficient Technologies -- Low Power Design Techniques for Contactless Chipcards -- Dynamic Memory Design for Low Data-Retention Power -- Double-Latch Clocking Scheme for Low-Power I.P. Cores -- Design of Multimedia Processing Applications -- Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip -- Cost-Efficient C-Level Design of an MPEG-4 Video Decoder -- Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications -- AdiabaticDesign and ArithmeticModules -- Design of Reversible Logic Circuits by Means of Control Gates -- Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates -- An Adiabatic Multiplier -- Logarithmic Number System for Low-Power Arithmetic -- Analog-Digital Circuits Modeling -- An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits -- PARCOURS — Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits -- Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits -- Computer Aided Generation of Analytic Models for Nonlinear Function Blocks.
650		0	_aComputer systems.
650		0	_aMicroprocessors.
650		0	_aComputer architecture.
650		0	_aComputer arithmetic and logic units.
650		0	_aLogic design.
650		0	_aElectronic digital computers _xEvaluation.
650		0	_aDynamics.
650		0	_aNonlinear theories.
650	1	4	_aComputer System Implementation.
650	2	4	_aProcessor Architectures.
650	2	4	_aArithmetic and Logic Structures.
650	2	4	_aLogic Design.
650	2	4	_aSystem Performance and Evaluation.
650	2	4	_aApplied Dynamical Systems.
700	1		_aSoudris, Dimitrios. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt
700	1		_aPirsch, Peter. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt
700	1		_aBarke, Erich. _eeditor. _4edt _4http://id.loc.gov/vocabulary/relators/edt
710	2		_aSpringerLink (Online service)
773	0		_tSpringer Nature eBook
776	0	8	_iPrinted edition: _z9783540410683
776	0	8	_iPrinted edition: _z9783662187272
830		0	_aLecture Notes in Computer Science, _x1611-3349 ; _v1918
856	4	0	_uhttps://doi.org/10.1007/3-540-45373-3
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