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020 _a9783540302056
_9978-3-540-30205-6
024 7 _a10.1007/b100662
_2doi
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_2bicssc
072 7 _aTEC008000
_2bisacsh
072 7 _aTJF
_2thema
082 0 4 _a621.381
_223
245 1 0 _aIntegrated Circuit and System Design
_h[electronic resource] :
_bPower and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings /
_cedited by Enrico Macii, Vassilis Paliouras, Odysseas Koufopavlou.
250 _a1st ed. 2004.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg :
_bImprint: Springer,
_c2004.
300 _aXVI, 916 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
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490 1 _aLecture Notes in Computer Science,
_x1611-3349 ;
_v3254
505 0 _aKeynote Speech -- Invited Talks -- Embedded Tutorials -- Session 1: Buses and Communication -- Session 2: Circuits and Devices (I) -- Session 3: Low Power (I) -- Session 4: Architectures -- Session 5: Asynchronous Circuits -- Session 6: System Design -- Session 7: Circuits and Devices (II) -- Session 8: Interconnect and Physical Design -- Session 9: Security and Safety -- Session 10: Low Power (II) -- Session 11: Low-Power Processing (Poster) -- Session 12: Digital Design (Poster) -- Session 13: Modeling and Simulation (Poster).
520 _aWelcometotheproceedingsofPATMOS2004,thefourteenthinaseriesofint- national workshops. PATMOS 2004 was organized by the University of Patras with technical co-sponsorship from the IEEE Circuits and Systems Society. Over the years, the PATMOS meeting has evolved into an important - ropean event, where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design. PATMOS provides a forum for researchers to discuss and investigate the emerging challenges in - sign methodologies and tools required to develop the upcoming generations of integrated circuits and systems. We realized this vision this year by providing a technical program that contained state-of-the-art technical contributions, a keynote speech, three invited talks and two embedded tutorials. The technical program focused on timing, performance and power consumption, as well as architectural aspects, with particular emphasis on modelling, design, charac- rization, analysis and optimization in the nanometer era. This year a record 152 contributions were received to be considered for p- sible presentation at PATMOS. Despite the choice for an intense three-day m- ting, only 51 lecture papers and 34 poster papers could be accommodated in the single-track technical program. The Technical Program Committee, with the - sistance of additional expert reviewers, selected the 85 papers to be presented at PATMOS and organized them into 13 technical sessions. As was the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were received per manuscript.
650 0 _aElectronics.
650 0 _aComputer science.
650 0 _aLogic design.
650 0 _aComputers.
650 0 _aMicroprocessors.
650 0 _aComputer architecture.
650 0 _aComputer arithmetic and logic units.
650 1 4 _aElectronics and Microelectronics, Instrumentation.
650 2 4 _aTheory of Computation.
650 2 4 _aLogic Design.
650 2 4 _aHardware Performance and Reliability.
650 2 4 _aProcessor Architectures.
650 2 4 _aArithmetic and Logic Structures.
700 1 _aMacii, Enrico.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aPaliouras, Vassilis.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aKoufopavlou, Odysseas.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
710 2 _aSpringerLink (Online service)
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783540230953
776 0 8 _iPrinted edition:
_z9783662169407
830 0 _aLecture Notes in Computer Science,
_x1611-3349 ;
_v3254
856 4 0 _uhttps://doi.org/10.1007/b100662
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