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020 _a9783540390978
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024 7 _a10.1007/11847083
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072 7 _aCOM014000
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072 7 _aUYA
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082 0 4 _a004.0151
_223
245 1 0 _aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
_h[electronic resource] :
_b16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings /
_cedited by Johan Vounckx, Nadine Azemard, Philippe Maurine.
250 _a1st ed. 2006.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg :
_bImprint: Springer,
_c2006.
300 _aXVI, 677 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
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490 1 _aTheoretical Computer Science and General Issues,
_x2512-2029 ;
_v4148
505 0 _aSession 1 – High-Level Design -- Session 2 – Power Estimation / Modeling -- Session 3 – Memory and Register Files -- Session 4 – Low-Power Digital Circuits -- Session 5 – Busses and Interconnects -- Session 6 – Low Power Techniques -- Session 7 – Applications and SoC Design -- Session 8 – Modeling -- Session 9 – Digital Circuits -- Session 10 – Reconfigurable and Programmable Devices -- Poster 1 -- Poster 2 -- Poster 3 -- Keynotes -- Industrial Session.
520 _aWelcome to the proceedings of PATMOS 2006, the 16th in a series of international workshops. PATMOS 2006 was organized by LIRMM with CAS technical - sponsorship and CEDA sponsorship. Over the years, the PATMOS workshop has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design methodologies, and tools required for the development of upcoming generations of integrated circuits and systems. The technical program of PATMOS 2006 contained state-of-the-art technical contributions, three invited talks, a special session on hearing-aid design, and an embedded tutorial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 64 papers presented at PATMOS. The papers were organized into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.
650 0 _aComputer science.
650 0 _aLogic design.
650 0 _aMicroprocessors.
650 0 _aComputer architecture.
650 0 _aElectronic digital computers
_xEvaluation.
650 0 _aComputer arithmetic and logic units.
650 0 _aComputer storage devices.
650 0 _aMemory management (Computer science).
650 1 4 _aTheory of Computation.
650 2 4 _aLogic Design.
650 2 4 _aProcessor Architectures.
650 2 4 _aSystem Performance and Evaluation.
650 2 4 _aArithmetic and Logic Structures.
650 2 4 _aComputer Memory Structure.
700 1 _aVounckx, Johan.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aAzemard, Nadine.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aMaurine, Philippe.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
710 2 _aSpringerLink (Online service)
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783540390947
776 0 8 _iPrinted edition:
_z9783540828747
830 0 _aTheoretical Computer Science and General Issues,
_x2512-2029 ;
_v4148
856 4 0 _uhttps://doi.org/10.1007/11847083
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