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020 _a9783540693383
_9978-3-540-69338-3
024 7 _a10.1007/978-3-540-69338-3
_2doi
050 4 _aQA75.5-76.95
072 7 _aUYA
_2bicssc
072 7 _aCOM014000
_2bisacsh
072 7 _aUYA
_2thema
082 0 4 _a004.0151
_223
245 1 0 _aHigh Performance Embedded Architectures and Compilers
_h[electronic resource] :
_bSecond International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings /
_cedited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer.
250 _a1st ed. 2007.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg :
_bImprint: Springer,
_c2007.
300 _aXI, 307 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aTheoretical Computer Science and General Issues,
_x2512-2029 ;
_v4367
505 0 _aInvited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints.
650 0 _aComputer science.
650 0 _aComputer arithmetic and logic units.
650 0 _aMicroprocessors.
650 0 _aComputer architecture.
650 0 _aComputer input-output equipment.
650 0 _aLogic design.
650 0 _aComputer networks .
650 1 4 _aTheory of Computation.
650 2 4 _aArithmetic and Logic Structures.
650 2 4 _aProcessor Architectures.
650 2 4 _aInput/Output and Data Communications.
650 2 4 _aLogic Design.
650 2 4 _aComputer Communication Networks.
700 1 _aDe Bosschere, Koen.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aKaeli, David.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aStenström, Per.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aWhalley, David.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
700 1 _aUngerer, Theo.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
710 2 _aSpringerLink (Online service)
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783540693376
776 0 8 _iPrinted edition:
_z9783540834571
830 0 _aTheoretical Computer Science and General Issues,
_x2512-2029 ;
_v4367
856 4 0 _uhttps://doi.org/10.1007/978-3-540-69338-3
912 _aZDB-2-SCS
912 _aZDB-2-SXCS
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