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001			978-3-031-18397-3
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005			20240423125126.0
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008			221108s2022 sz | s |||| 0|eng d
020			_a9783031183973 _9978-3-031-18397-3
024	7		_a10.1007/978-3-031-18397-3 _2doi
050		4	_aTK7867-7867.5
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
072		7	_aTJFC _2thema
082	0	4	_a621.3815 _223
100	1		_aSrivastava, Pallavi. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut
245	1	0	_aCompletion Detection in Asynchronous Circuits _h[electronic resource] : _bToward Solution of Clock-Related Design Challenges / _cby Pallavi Srivastava.
250			_a1st ed. 2022.
264		1	_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2022.
300			_aXV, 119 p. 65 illus., 51 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aIntroduction to asynchronous circuit design -- "Preliminary considerations for asynchronous circuit design." -- "Completion detection schemes for asynchronous design style" -- Case Studies: Barrel shifter and binary adders -- "Generic Architecture of deterministic completion detection scheme" -- Architecture optimization using deterministic completion detection" -- Simulations.
520			_aThis book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits. Analyzes circuit design techniques in the context of timing constraints; Develops a generic, deterministic completion detection scheme for asynchronous circuits using bundled data protocol; Demonstrates a single-precision, asynchronous bundled data barrel shifter to validate the completion detection scheme.
650		0	_aElectronic circuits.
650		0	_aElectronic circuit design.
650		0	_aMicroprocessors.
650		0	_aComputer architecture.
650	1	4	_aElectronic Circuits and Systems.
650	2	4	_aElectronics Design and Verification.
650	2	4	_aProcessor Architectures.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer Nature eBook
776	0	8	_iPrinted edition: _z9783031183966
776	0	8	_iPrinted edition: _z9783031183980
776	0	8	_iPrinted edition: _z9783031183997
856	4	0	_uhttps://doi.org/10.1007/978-3-031-18397-3
912			_aZDB-2-SCS
912			_aZDB-2-SXCS
942			_cSPRINGER
999			_c174529 _d174529