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001 978-3-540-48153-9
003 DE-He213
005 20170515111506.0
007 cr nn 008mamaa
008 121227s1999 gw | s |||| 0|eng d
020 _a9783540481539
_9978-3-540-48153-9
024 7 _a10.1007/3-540-48153-2
_2doi
050 4 _aQA76.9.A73
050 4 _aQA76.9.S88
072 7 _aUYD
_2bicssc
072 7 _aCOM032000
_2bisacsh
072 7 _aCOM067000
_2bisacsh
082 0 4 _a003.3
_223
245 1 0 _aCorrect Hardware Design and Verification Methods
_h[electronic resource] :
_b10th IFIP WG10.5 Advanced Research Working Conference, CHARME’99 BadHerrenalb,Germany,September 27–29, 1999 Proceedings /
_cedited by Laurence Pierre, Thomas Kropf.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg,
_c1999.
300 _aXII, 376 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v1703
505 0 _aInvited Talks -- Esterel and Jazz : Two Synchronous Languages for Circuit Design -- Design Process of Embedded Automotive Systems—Using Model Checking for Correct Specifications -- Proof of Microprocessors -- A Proof of Correctness of a Processor Implementing Tomasulo’s Algorithm without a Reorder Buffer -- Formal Verification of Explicitly Parallel Microprocessors -- Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic -- Model Checking -- Model Checking TLA+ Specifications -- Efficient Decompositional Model Checking for Regular Timing Diagrams -- Vacuity Detection in Temporal Model Checking -- Formal Methods and Industrial Applications -- Using Symbolic Model Checking to Verify the Railway Stations of Hoorn-Kersenboogerd and Heerhugowaard -- Practical Application of Formal Verification Techniques on a Frame Mux/Demux Chip from Nortel Semiconductors -- Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics -- Abstraction and Compositional Techniques -- From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking -- Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction -- Abstract BDDs: A Technique for Using Abstraction in Model Checking -- Theorem Proving Related Approaches -- Formal Synthesis at the Algorithmic Level -- Xs Are for Trajectory Evaluation, Booleans Are for Theorem Proving -- Verification of Infinite State Systems by Compositional Model Checking -- Symbolic Simulation/Symbolic Traversal -- Formal Verification of Designs with Complex Control by Symbolic Simulation -- Hints to Accelerate Symbolic Traversal -- Specification Languages and Methodologies -- Modeling and Checking Networks of Communicating Real-Time Processes -- ”Have I Written Enough Properties?” - A Method of Comparison Between Specification and Implementation -- Program Slicing of Hardware Description Languages -- Posters -- Results of the Verification of a Complex Pipelined Machine Model -- Hazard—Freedom Checking in Speed—Independent Systems -- Yet Another Look at LTL Model Checking -- Verification of Finite-State-Machine Refinements Using a Symbolic Methodology -- Refinement and Property Checking in High-Level Synthesis Using Attribute Grammars -- A Systematic Incrementalization Technique and Its Application to Hardware Design -- Bisimulation and Model Checking -- Circular Compositional Reasoning about Liveness -- Symbolic Simulation of Microprocessor Models Using Type Classes in Haskell -- Exploiting Retiming in a Guided Simulation Based Validation Methodology -- Fault Models for Embedded Systems -- Validation of Object-Oriented Concurrent Designs by Model Checking.
520 _aCHARME’99 is the tenth in a series of working conferences devoted to the dev- opment and use of leading-edge formal techniques and tools for the design and veri?cation of hardware and systems. Previous conferences have been held in Darmstadt (1984), Edinburgh (1985), Grenoble (1986), Glasgow (1988), Leuven (1989), Torino (1991), Arles (1993), Frankfurt (1995) and Montreal (1997). This workshop and conference series has been organized in cooperation with IFIP WG 10. 5. It is now the biannual counterpart of FMCAD, which takes place every even-numbered year in the USA. The 1999 event took place in Bad Her- nalb, a resort village located in the Black Forest close to the city of Karlsruhe. The validation of functional and timing behavior is a major bottleneck in current VLSI design systems. A predominantly academic area of study until a few years ago, formal design and veri?cation techniques are now migrating into industrial use. The aim of CHARME’99 is to bring together researchers and users from academia and industry working in this active area of research. Two invited talks illustrate major current trends: the presentation by G´erard Berry (Ecole des Mines de Paris, Sophia-Antipolis, France) is concerned with the use of synchronous languages in circuit design, and the talk given by Peter Jansen (BMW, Munich, Germany) demonstrates an application of formal methods in an industrial environment. The program also includes 20 regular presentations and 12 short presentations/poster exhibitions that have been selected from the 48 submitted papers.
650 0 _aComputer science.
650 0 _aComputer hardware.
650 0 _aArchitecture, Computer.
650 0 _aSoftware engineering.
650 0 _aComputer logic.
650 0 _aComputer engineering.
650 0 _aComplexity, Computational.
650 1 4 _aComputer Science.
650 2 4 _aComputer System Implementation.
650 2 4 _aComputer Engineering.
650 2 4 _aComputer Hardware.
650 2 4 _aLogics and Meanings of Programs.
650 2 4 _aSoftware Engineering.
650 2 4 _aComplexity.
700 1 _aPierre, Laurence.
_eeditor.
700 1 _aKropf, Thomas.
_eeditor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783540665595
830 0 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v1703
856 4 0 _uhttp://dx.doi.org/10.1007/3-540-48153-2
912 _aZDB-2-SCS
912 _aZDB-2-LNC
912 _aZDB-2-BAE
942 _2ddc
_cEB
950 _aComputer Science (Springer-11645)
999 _c14679
_d14679