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Verilog HDL synthesis : a practical primer

By:

Bhasker, J

Material type: Text

Text

TextPublication details: BSP, ©2008. New Delhi:Description: 216 pISBN:

9788120323667

Subject(s):

DDC classification:

621.392 BHA-V

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Holdings ( 5 )
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Holdings
Item type	Current library	Collection	Call number	Status	Date due	Barcode	Item holds	Course reserves
Books	IIITD General Stacks	Electronics and Communication Engineering	621.392 BHA-V (Browse shelf(Opens below))	Available		000657
Books	IIITD General Stacks	Electronics and Communication Engineering	621.392 BHA-V (Browse shelf(Opens below))	Available		000658
Books	IIITD General Stacks	Electronics and Communication Engineering	621.392 BHA-V (Browse shelf(Opens below))	Available		000659
Books	IIITD General Stacks	Electronics and Communication Engineering	621.392 BHA-V (Browse shelf(Opens below))	Available		000660
Reference	IIITD Reference	Electronics and Communication Engineering	REF 621.392 BHA-V (Browse shelf(Opens below))	Not for loan		000661		VLSI Design Flow UG/PG (REST) WNT24

Total holds: 0

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