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Low power design methodologies

By: Material type: TextTextPublication details: New Delhi.: Springer, ©1996.Description: x, 367 p. : ill. ; 25 cmISBN:
  • 9788184895063
Subject(s): DDC classification:
  • 621.392 20 RAB-L
LOC classification:
  • TK7871.99.M44 R33 1996
Online resources:
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Holdings
Item type Current library Collection Call number Status Date due Barcode Item holds
Books Books IIITD Reference Electronics and Communication Engineering REF 621.392 RAB-L (Browse shelf(Opens below)) Available 004290
Total holds: 0
Browsing IIITD shelves, Shelving location: Reference, Collection: Electronics and Communication Engineering Close shelf browser (Hides shelf browser)
REF 621.392 BHA-V Verilog HDL synthesis : REF 621.392 BHA-V A Verilog HDL primer REF 621.392 PAL-V Verilog HDL : a guide to digital design and synthesis REF 621.392 RAB-L Low power design methodologies REF 621.392 SPE-S SystemVerilog for verification : REF 621.392 VAH-D Digital design REF 621.395 BAL-D Digital logic design principles

Includes bibliographical references and indexes.

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