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Writing testbenches using system verilog

By: Bergeron, Janick.
Contributor(s): Bergeron, Janick. Writing testbenches, functional verification of HDL models.
Material type: materialTypeLabelBookPublisher: New Delhi : Springer, c2006Description: xxvi, 412 p. : ill. ; 25 cm.ISBN: 0387292217; 9788184892697.Subject(s): Computer hardware description languages | Integrated circuits -- VerificationOnline resources: Publisher description | Table of contents only
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Electronics and Communication Engineering 621.392 BER-W (Browse shelf) Available 002733
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This book presents the same concepts as the second edition of Writing testbenches, functional verification of HDL models, but uses System Verilog as the sole implementation vehicle. The languages used in the second edition are still available.

Includes bibliographical references and index.

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