Writing testbenches using system verilog
By: Bergeron, Janick.Material type: BookPublisher: New Delhi : Springer, c2006Description: xxvi, 412 p. : ill. ; 25 cm.ISBN: 0387292217; 9788184892697.Subject(s): Computer hardware description languages | Integrated circuits -- VerificationOnline resources: Publisher description | Table of contents only
|Item type||Current location||Collection||Call number||Status||Date due||Barcode||Item holds|
|Books||IIITD General Stacks||Electronics and Communication Engineering||621.392 BER-W (Browse shelf)||Available||002733|
This book presents the same concepts as the second edition of Writing testbenches, functional verification of HDL models, but uses System Verilog as the sole implementation vehicle. The languages used in the second edition are still available.
Includes bibliographical references and index.