FEEDBACK Smiley face
Normal view MARC view ISBD view

Writing testbenches using system verilog

By: Bergeron, Janick.
Contributor(s): Bergeron, Janick. Writing testbenches, functional verification of HDL models.
Material type: materialTypeLabelBookPublisher: New Delhi : Springer, c2006Description: xxvi, 412 p. : ill. ; 25 cm.ISBN: 0387292217; 9788184892697.Subject(s): Computer hardware description languages | Integrated circuits -- VerificationOnline resources: Publisher description | Table of contents only
Tags from this library: No tags from this library for this title. Add tag(s)
Log in to add tags.
    average rating: 0.0 (0 votes)
Item type Current location Collection Call number Status Date due Barcode Item holds
Books Books IIITD
General Stacks
Electronics and Communication Engineering 621.392 BER-W (Browse shelf) Available 002733
Total holds: 0

This book presents the same concepts as the second edition of Writing testbenches, functional verification of HDL models, but uses System Verilog as the sole implementation vehicle. The languages used in the second edition are still available.

Includes bibliographical references and index.

There are no comments for this item.

Log in to your account to post a comment.

© IIIT-Delhi, 2013 | Phone: +91-11-26907510| FAX +91-11-26907405 | E-mail: