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Computer architecture : pipelined and parallel processor design

By: Material type: TextTextPublication details: New Delhi : Narosa, c1995.Description: xix, 788 p. : ill. ; 26 cmISBN:
  • 9788173191008
Subject(s): DDC classification:
  • 004.22 20 FLY-C
LOC classification:
  • QA76.9.A73 F58 1995
Contents:
1. Architecture and Machines -- 2. Time, Area, and Instruction Sets -- 3. Data: How Programs Behave -- 4. Pipelined Processor Design -- 5. Cache Memory -- 6. Memory System Design -- 7. Concurrent Processors -- 8. Shared Memory Multiprocessors -- 9. I/O and the Storage Hierarchy -- 10. Processor Studies -- Appendix A DTMR Cache Miss Rates -- Appendix B SPECmark vs. DTMR Cache Performance -- Appendix C Modeling System Effects in Caches -- Appendix D New DRAM Technologies -- Appendix E M/G/1 Queues -- Appendix F Some Details on Bus-Based Protocols.
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Holdings
Item type Current library Collection Call number Status Date due Barcode Item holds
Books Books IIITD General Stacks Computer Science and Engineering 004.22 FLY-C (Browse shelf(Opens below)) Available 001355
Books Books IIITD Reference Computer Science and Engineering REF 004.22 FLY-C (Browse shelf(Opens below)) Available 001356
Total holds: 0
Browsing IIITD shelves, Shelving location: Reference, Collection: Computer Science and Engineering Close shelf browser (Hides shelf browser)
REF 004.21 CAL-O The Oxford handbook of affective computing REF 004.21 GRO-S System design with system C REF 004.22 COM-E Essentials of computer architecture REF 004.22 FLY-C Computer architecture : REF 004.22 HAM-C Computer organization and embedded systems REF 004.22 HAM-C Computer organization REF 004.22 HAY-C Computer architecture and organization

Includes bibliographical references and index.

1. Architecture and Machines -- 2. Time, Area, and Instruction Sets -- 3. Data: How Programs Behave -- 4. Pipelined Processor Design -- 5. Cache Memory -- 6. Memory System Design -- 7. Concurrent Processors -- 8. Shared Memory Multiprocessors -- 9. I/O and the Storage Hierarchy -- 10. Processor Studies -- Appendix A DTMR Cache Miss Rates -- Appendix B SPECmark vs. DTMR Cache Performance -- Appendix C Modeling System Effects in Caches -- Appendix D New DRAM Technologies -- Appendix E M/G/1 Queues -- Appendix F Some Details on Bus-Based Protocols.

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