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SystemVerilog for verification : a guide to learning the testbench language features
Material type:
TextPublication details: New York : Springer, ©2012.Edition: 3rd edDescription: xliii, 464 p. : ill. ; 24 cmISBN: - 9781489995001
- 621.392 SPE-S
| Item type | Current library | Collection | Call number | Status | Date due | Barcode | Item holds | Course reserves |
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Reference
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IIITD Reference | Electronics and Communication Engineering | REF 621.392 SPE-S (Browse shelf(Opens below)) | Checked out Not for loan | 22/05/2024 | 010125 |
Total holds: 0
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| REF 621.392 BHA-V A Verilog HDL primer | REF 621.392 PAL-V Verilog HDL : | REF 621.392 RAB-L Low power design methodologies | REF 621.392 SPE-S SystemVerilog for verification : | REF 621.392 VAH-D Digital design | REF 621.395 BAL-D Digital logic design principles | REF 621.395 BRO-F Fundamentals of digital logic design with VHDL |
Includes bibliographical references and index.
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