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Reconfigurable Computing: Architectures, Tools and Applications (Record no. 17459)

000 -LEADER
fixed length control field 05546nam a22006375i 4500
001 - CONTROL NUMBER
control field 978-3-540-71431-6
003 - CONTROL NUMBER IDENTIFIER
control field DE-He213
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20170515111636.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 100301s2007 gw | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9783540714316
-- 978-3-540-71431-6
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/978-3-540-71431-6
Source of number or code doi
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number QA75.5-76.95
072 #7 - SUBJECT CATEGORY CODE
Subject category code UY
Source bicssc
072 #7 - SUBJECT CATEGORY CODE
Subject category code UYA
Source bicssc
072 #7 - SUBJECT CATEGORY CODE
Subject category code COM014000
Source bisacsh
072 #7 - SUBJECT CATEGORY CODE
Subject category code COM031000
Source bisacsh
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 004.0151
Edition number 23
245 10 - TITLE STATEMENT
Title Reconfigurable Computing: Architectures, Tools and Applications
Medium [electronic resource] :
Remainder of title Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007. Proceedings /
Statement of responsibility, etc edited by Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, João M. P. Cardoso.
264 #1 -
-- Berlin, Heidelberg :
-- Springer Berlin Heidelberg,
-- 2007.
300 ## - PHYSICAL DESCRIPTION
Extent XIV, 394 p.
Other physical details online resource.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
490 1# - SERIES STATEMENT
Series statement Lecture Notes in Computer Science,
International Standard Serial Number 0302-9743 ;
Volume number/sequential designation 4419
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Architectures [Regular Papers] -- Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array -- A Configurable Multi-ported Register File Architecture for Soft Processor Cores -- MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture -- Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture -- Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs -- Systematic Customization of On-Chip Crossbar Interconnects -- Authentication of FPGA Bitstreams: Why and How -- Architectures [Short Papers] -- Design of a Reversible PLD Architecture -- Designing Heterogeneous FPGAs with Multiple SBs -- Mapping Techniques and Tools [Regular Papers] -- Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations -- Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware -- Adapting and Automating XILINX’s Partial Reconfiguration Flow for Multiple Module Implementations -- A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions -- Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping -- The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining -- Hardware/Software Codesign for Embedded Implementation of Neural Networks -- Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues -- Mapping Techniques and Tools [Short Papers] -- About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations -- Arithmetic [Regular Papers] -- Switching Activity Models for Power Estimation in FPGA Multipliers -- Multiplication over on FPGA: A Survey -- A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm -- A Fast Finite Field Multiplier -- Applications [Regular Papers] -- Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval -- Image Processing Architecture for Local Features Computation -- A Compact Shader for FPGA-Based Volume Rendering Accelerators -- Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications -- FPGA-Accelerated Molecular Dynamics Simulations: An Overview -- Reconfigurable Hardware Acceleration of Canonical Graph Labelling -- Reconfigurable Computing for Accelerating Protein Folding Simulations -- Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits -- Applications [Short Papers] -- A Space Variant Mapping Architecture for Reliable Car Segmentation -- A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads -- Searching the Web with an FPGA Based Search Engine -- An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner’s Dilemma -- Real Time Architectures for Moving-Objects Tracking -- Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller -- Multiple Sequence Alignment Using Reconfigurable Computing -- Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer science.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer hardware.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Microprocessors.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer communication systems.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer system failures.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Architecture, Computer.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computers.
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer Science.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Theory of Computation.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer Hardware.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Processor Architectures.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer Communication Networks.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element System Performance and Evaluation.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer System Implementation.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Diniz, Pedro C.
Relator term editor.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Marques, Eduardo.
Relator term editor.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Bertels, Koen.
Relator term editor.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Fernandes, Marcio Merino.
Relator term editor.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Cardoso, João M. P.
Relator term editor.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9783540714309
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Lecture Notes in Computer Science,
-- 0302-9743 ;
Volume number/sequential designation 4419
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.1007/978-3-540-71431-6
912 ## -
-- ZDB-2-SCS
912 ## -
-- ZDB-2-LNC
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme
Koha item type e-Book

No items available.


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