MARC details
| 000 -LEADER |
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| fixed length control field |
01944nam a22002657a 4500 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
IIITD |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20240501020004.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
230606b xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9781009200813 |
| 040 ## - CATALOGING SOURCE |
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| Original cataloging agency |
IIITD |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.395 |
| Item number |
SAU-I |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Saurabh, Sneh |
| 245 ## - TITLE STATEMENT |
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| Title |
Introduction to VLSI design flow |
| Statement of responsibility, etc |
by Sneh Saurabh |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Name of publisher, distributor, etc |
Cambridge University Press, |
| Place of publication, distribution, etc |
New York : |
| Date of publication, distribution, etc |
©2023 |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
xxiv, 689 p. |
| Dimensions |
24 cm. |
| 500 ## - GENERAL NOTE |
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| General note |
This book includes an index. |
| 505 ## - FORMATTED CONTENTS NOTE |
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| Title |
Part I. Overview of VLSI Design Flow: Chapter 1. Foundation |
| -- |
Chapter 2. Introduction to Integrated Circuits |
| -- |
Chapter 3. Pre-RTL Methodologies |
| -- |
Chapter 4. RTL to GDS Implementation Flow |
| -- |
Chapter 5. Verification Techniques |
| -- |
Chapter 6. Testing Techniques |
| -- |
Chapter 7. Post-GDS Processes |
| -- |
Part II. Logic Design: Chapter 8. Modeling Hardware using Verilog |
| -- |
Chapter 9. Simulation-based Verification |
| -- |
Chapter 10. RTL Synthesis |
| -- |
Chapter 11. Formal Verification, Chapter 12. Logic Optimization |
| -- |
Chapter 13. Technology Library |
| -- |
Chapter 14. Static Timing Analysis |
| -- |
Chapter 15. Constraints |
| -- |
Chapter 16. Technology Mapping |
| -- |
Chapter 17. Timing-driven Optimizations |
| -- |
Chapter 18. Power Analysis |
| -- |
Chapter 19. Power-driven Optimizations |
| -- |
Part III. Design for Testability (DFT): Chapter 20. Basics of DFT |
| -- |
Chapter 21. Scan Design |
| -- |
Chapter 22. Automatic Test Pattern Generation (ATPG) |
| -- |
Chapter 23. Built-in Self-test (BIST) |
| -- |
Part IV. Physical Design: Chapter 24. Basic Concepts for Physical Design |
| -- |
Chapter 25. Chip Planning |
| -- |
Chapter 26. Placement |
| -- |
Chapter 27. Clock Tree Synthesis (CTS) |
| -- |
Chapter 28. Routing |
| -- |
Chapter 29. Physical Verification and Signoff |
| -- |
Chapter 30. Post-silicon Validation. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
VLSI |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Integrated circuits |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Very large scale integration |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Design and construction |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Metal oxide semiconductors |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Complementary |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Books |
| Koha issues (borrowed), all copies |
12 |
