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Integrated Circuit Design (Record no. 14981)

000 -LEADER
fixed length control field 04997nam a22006255i 4500
001 - CONTROL NUMBER
control field 978-3-540-45373-4
003 - CONTROL NUMBER IDENTIFIER
control field DE-He213
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20170515111519.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 121227s2000 gw | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9783540453734
-- 978-3-540-45373-4
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/3-540-45373-3
Source of number or code doi
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number QA76.9.A73
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number QA76.9.S88
072 #7 - SUBJECT CATEGORY CODE
Subject category code UYD
Source bicssc
072 #7 - SUBJECT CATEGORY CODE
Subject category code COM032000
Source bisacsh
072 #7 - SUBJECT CATEGORY CODE
Subject category code COM067000
Source bisacsh
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 003.3
Edition number 23
245 10 - TITLE STATEMENT
Title Integrated Circuit Design
Medium [electronic resource] :
Remainder of title Power and Timing Modeling, Optimization and Simulation 10th International Workshop,PATMOS 2000 Göttingen, Germany, September 13–15, 2000 Proceedings /
Statement of responsibility, etc edited by Dimitrios Soudris, Peter Pirsch, Erich Barke.
264 #1 -
-- Berlin, Heidelberg :
-- Springer Berlin Heidelberg,
-- 2000.
300 ## - PHYSICAL DESCRIPTION
Extent XII, 338 p.
Other physical details online resource.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
490 1# - SERIES STATEMENT
Series statement Lecture Notes in Computer Science,
International Standard Serial Number 0302-9743 ;
Volume number/sequential designation 1918
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Opening -- Constraints, Hurdles and Opportunities for a Successful European Take-Up Action -- RTL Power Modeling -- Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques -- Power Models for Semi-autonomous RTL Macros -- Power Macro-Modelling for Firm-Macro -- RTL Estimation of Steering Logic Power -- Power Estimation and Optimization -- Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers -- Framework for High-Level Power Estimation of Signal Processing Architectures -- Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses -- Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions -- System-Level Design -- A Holistic Approach to System Level Energy Optimization -- Early Power Estimation for System-on-Chip Designs -- Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures -- Transistor-Level Modeling -- Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design -- Impact of Voltage Scaling on Glitch Power Consumption -- Degradation Delay Model Extension to CMOS Gates -- Second Generation Delay Model for Submicron CMOS Process -- Asynchronous Circuit Design -- Semi-modular Latch Chains for Asynchronous Circuit Design -- Asynchronous First-in First-out Queues -- Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance -- VLSI Implementation of a Low-Power High-Speed Self-Timed Adder -- Power Efficient Technologies -- Low Power Design Techniques for Contactless Chipcards -- Dynamic Memory Design for Low Data-Retention Power -- Double-Latch Clocking Scheme for Low-Power I.P. Cores -- Design of Multimedia Processing Applications -- Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip -- Cost-Efficient C-Level Design of an MPEG-4 Video Decoder -- Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications -- AdiabaticDesign and ArithmeticModules -- Design of Reversible Logic Circuits by Means of Control Gates -- Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates -- An Adiabatic Multiplier -- Logarithmic Number System for Low-Power Arithmetic -- Analog-Digital Circuits Modeling -- An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits -- PARCOURS — Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits -- Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits -- Computer Aided Generation of Analytic Models for Nonlinear Function Blocks.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer science.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Arithmetic and logic units, Computer.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Logic design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Microprocessors.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer system failures.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Architecture, Computer.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Complexity, Computational.
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer Science.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer System Implementation.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Processor Architectures.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Arithmetic and Logic Structures.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Logic Design.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element System Performance and Evaluation.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Complexity.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Soudris, Dimitrios.
Relator term editor.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Pirsch, Peter.
Relator term editor.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Barke, Erich.
Relator term editor.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9783540410683
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Lecture Notes in Computer Science,
-- 0302-9743 ;
Volume number/sequential designation 1918
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.1007/3-540-45373-3
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-- ZDB-2-BAE
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme
Koha item type e-Book

No items available.


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