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Field Programmable Logic and Applications (Record no. 14706)

000 -LEADER
fixed length control field 08443nam a22006135i 4500
001 - CONTROL NUMBER
control field 978-3-540-48302-1
003 - CONTROL NUMBER IDENTIFIER
control field DE-He213
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20170515111507.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 121227s1999 gw | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9783540483021
-- 978-3-540-48302-1
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/b72332
Source of number or code doi
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number QA76.9.A73
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number QA76.9.S88
072 #7 - SUBJECT CATEGORY CODE
Subject category code UYD
Source bicssc
072 #7 - SUBJECT CATEGORY CODE
Subject category code COM032000
Source bisacsh
072 #7 - SUBJECT CATEGORY CODE
Subject category code COM067000
Source bisacsh
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 003.3
Edition number 23
245 10 - TITLE STATEMENT
Title Field Programmable Logic and Applications
Medium [electronic resource] :
Remainder of title 9th International Workshop, FPL’99, Glasgow, UK, August 30 - September 1, 1999. Proceedings /
Statement of responsibility, etc edited by Patrick Lysaght, James Irvine, Reiner Hartenstein.
264 #1 -
-- Berlin, Heidelberg :
-- Springer Berlin Heidelberg,
-- 1999.
300 ## - PHYSICAL DESCRIPTION
Extent XII, 552 p.
Other physical details online resource.
336 ## -
-- text
-- txt
-- rdacontent
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-- computer
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-- rdamedia
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-- online resource
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347 ## -
-- text file
-- PDF
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490 1# - SERIES STATEMENT
Series statement Lecture Notes in Computer Science,
International Standard Serial Number 0302-9743 ;
Volume number/sequential designation 1673
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Signal Processing -- Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing -- Auditory Signal Processing in Hardware -- SONIC – A Plug-In Architecture for Video Processing -- CAD Tools for DRL -- DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems -- Modelling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems Using the DCS CAD Framework -- Optimization Studies -- Optimal Finite Field Multipliers for FPGAs -- Memory Access Optimization and RAM Inference for Pipeline Vectorization -- Analysis and Optimization of 3-D FPGA Design Parameters -- Physical Design -- Tabu Search: Ultra-Fast Placement for FPGAs -- Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies -- Hierarchical Interactive Approach to Partition Large Designs into FPGAs -- Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays -- Dynamically Reconfigurable Logic -- DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems -- A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic -- Self Controlling Dynamic Reconfiguration: A Case Study -- Design Tools -- An Internet Based Development Framework for Reconfigurable Computing -- On Tool Integration in High-Performance FPGA Design Flows -- Hardware-Software Codesign for Dynamically Reconfigurable Architectures -- Reconfigurable Computing -- Serial Hardware Libraries for Reconfigurable Designs -- Reconfigurable Computing in Remote and Harsh Environments -- Communication Synthesis for Reconfigurable Embedded Systems -- Run-Time Parameterizable Cores -- Applications -- Rendering PostScript TM Fonts on FPGAs -- Implementing PhotoShopTM Filters in VirtexTM -- Rapid FPGA Prototyping of a DAB Test Data Generator Using Protocol Compiler -- Quantitative Analysis of Run-Time Reconfigurable Database Search -- Novel Architectures -- An On-Line Arithmetic Based FPGA for Low-Power Custom Computing -- A New Switch Block for Segmented FPGAs -- PulseDSP – A Signal Processing Oriented Programmable Architecture -- Machine Applications -- FPGA Viruses -- Genetic Programming Using Self-Reconfigurable FPGAs -- Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs -- Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs -- Short Papers -- An FPGA-Based Prototyping System for Real-Time Verification of Video Processing Schemes -- An FPGA Implementation of Goertzel Algorithm -- Pipelined Multipliers and FPGA Architectures -- FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding -- Reconfigurable Multiplier for Virtex FPGA Family -- Pipelined Floating Point Arithmetic Optimised for FPGA Architectures -- SL – A Structural Hardware Design Language -- High-Level Hierarchical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules -- Mapping Applications onto Reconfigurable KressArrays -- Global Routing Models -- Power Modelling in Field Programmable Gate Arrays (FPGA) -- NEBULA: A Partially and Dynamically Reconfigurable Architecture -- High Bandwidth Dynamically Reconfigurable Architectures Using Optical Interconnects -- AHA-GRAPE: Adaptive Hydrodynamic Architecture – GRAvity PipE -- DIME – The First Module Standard for FPGA Based High Performance Computing -- The Proteus Processor — A Conventional CPU with Reconfigurable Functionality -- Logic Circuit Speeding up through Multiplexing -- A Wildcarding Mechanism for Acceleration of Partial Configurations -- Hardware Implementation Techniques for Recursive Calls and Loops -- A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation -- An Alternative Solution for Reconfigurable Coprocessors Hardware and Interface Synthesis -- Reconfigurable Programming in the Large on Extendable Uniform Reconfigurable Computing Array’s: An Integrated Approach Based on Reconfigurable Virtual Architectures -- A Concept for an Evaluation Framework for Reconfigurable Systems -- Debugging Application-Specific Programmable Products -- IP Validation for FPGAs Using Hardware Object TechnologyTM -- A Processor for Artificial Life Simulation -- A Distributed, Scalable, Multi-layered Approach to Evolvable System Design Using FPGA’s -- Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching -- A Reconfigurable Architecture for High Speed Computation by Pipeline Processing -- Seeking (the Right) Problems for the Solutions of Reconfigurable Computing -- A Runtime Reconfigurable Implementation of the GSAT Algorithm -- Accelerating Boolean Implications with FPGAs.
520 ## - SUMMARY, ETC.
Summary, etc This book contains the papers presented at the 9th International Workshop on Field ProgrammableLogic and Applications (FPL’99), hosted by the University of Strathclyde in Glasgow, Scotland, August 30 – September 1, 1999. FPL’99 is the ninth in the series of annual FPL workshops. The FPL’99 programme committee has been fortunate to have received a large number of high-quality papers addressing a wide range of topics. From these, 33 papers have been selected for presentation at the workshop and a further 32 papers have been accepted for the poster sessions. A total of 65 papers from 20 countries are included in this volume. FPL is a subject area that attracts researchers from both electronic engine- ing and computer science. Whether we are engaged in research into soft ha- ware or hard software seems to be primarily a question of perspective. What is unquestionable is that the interaction of groups of researchers from di?erent backgrounds results in stimulating and productive research. As we prepare for the new millennium, the premier European forum for - searchers in ?eld programmable logic remains the FPL workshop. Next year the FPL series of workshopswill celebrate its tenth anniversary.The contribution of so many overseas researchers has been a particularly attractive feature of these events, giving them a truly international perspective, while the informal and convivial atmosphere that pervades the workshops have been their hallmark. We look forward to preserving these features in the future while continuing to expand the size and quality of the events.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer science.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Arithmetic and logic units, Computer.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Logic design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Microprocessors.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Architecture, Computer.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Complexity, Computational.
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer Science.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer System Implementation.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Logic Design.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Arithmetic and Logic Structures.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Processor Architectures.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Complexity.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Lysaght, Patrick.
Relator term editor.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Irvine, James.
Relator term editor.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Hartenstein, Reiner.
Relator term editor.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9783540664574
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Lecture Notes in Computer Science,
-- 0302-9743 ;
Volume number/sequential designation 1673
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.1007/b72332
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942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme
Koha item type e-Book

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