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High Performance Computing - HiPC 2003 10th International Conference, Hyderabad, India, December 17-20, 2003. Proceedings / [electronic resource] : edited by Timothy Mark Pinkston, Viktor K. Prasanna. - XX, 512 p. online resource. - Lecture Notes in Computer Science, 2913 0302-9743 ; . - Lecture Notes in Computer Science, 2913 .

Keynote Address -- Life’s Duplicities: Sex, Death, and Valis -- Session I – Performance Issues and Power-Aware Architectures -- Performance Analysis of Blue Gene/L Using Parallel Discrete Event Simulation -- An Efficient Web Cache Replacement Policy -- Timing Issues of Operating Mode Switch in High Performance Reconfigurable Architectures -- Power-Aware Adaptive Issue Queue and Register File -- FV-MSB: A Scheme for Reducing Transition Activity on Data Buses -- Session II – Parallel/Distributed and Network Algorithms -- A Parallel Iterative Improvement Stable Matching Algorithm -- Self-Stabilizing Distributed Algorithm for Strong Matching in a System Graph -- Parallel Data Cube Construction: Algorithms, Theoretical Analysis, and Experimental Evaluation -- Efficient Algorithm for Embedding Hypergraphs in a Cycle -- Mapping Hypercube Computations onto Partitioned Optical Passive Star Networks -- Keynote Address -- The High Performance Microprocessor in the Year 2013: What Will It Look Like? What It Won’t Look Like? -- Session III – Routing in Wireless, Mobile, and Cut-Through Networks -- FROOTS – Fault Handling in Up*/Down* Routed Networks with Multiple Roots -- Admission Control for DiffServ Based Quality of Service in Cut-Through Networks -- On Shortest Path Routing Schemes for Wireless Ad Hoc Networks -- A Hierarchical Routing Method for Load-Balancing -- Ring Based Routing Schemes for Load Distribution and Throughput Improvement in Multihop Cellular, Ad hoc, and Mesh Networks -- Session IV – Scientific and Engineering Applications -- A High Performance Computing System for Medical Imaging in the Remote Operating Room -- Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification -- Parallel and Distributed Frequent Itemset Mining on Dynamic Datasets -- A Volumetric FFT for BlueGene/L -- A Nearly Linear-Time General Algorithm for Genome-Wide Bi-allele Haplotype Phasing -- Keynote Address -- Energy Aware Algorithm Design via Probabilistic Computing: From Algorithms and Models to Moore’s Law and Novel (Semiconductor) Devices -- Session V – System Support in Overlay Networks, Clusters, and Grid -- Designing SANs to Support Low-Fanout Multicasts -- POMA: Prioritized Overlay Multicast in Ad Hoc Environments -- Supporting Mobile Multimedia Services with Intermittently Available Grid Resources -- Exploiting Non-blocking Remote Memory Access Communication in Scientific Benchmarks -- Session VI – Scheduling and Software Algorithms -- Scheduling Directed A-Cyclic Task Graphs on Heterogeneous Processors Using Task Duplication -- Double-Loop Feedback-Based Scheduling Approach for Distributed Real-Time Systems -- Combined Scheduling of Hard and Soft Real-Time Tasks in Multiprocessor Systems -- An Efficient Algorithm to Compute Delay Set in SPMD Programs -- Dynamic Load Balancing for I/O-Intensive Tasks on Heterogeneous Clusters -- Keynote Address -- Standards Based High Performance Computing -- Session VII – Network Design and Performance Issues -- Delay and Jitter Minimization in High Performance Internet Computing -- An Efficient Heuristic Search for Optimal Wavelength Requirement in Static WDM Optical Networks -- Slot Allocation Schemes for Delay Sensitive Traffic Support in Asynchronous Wireless Mesh Networks -- Multicriteria Network Design Using Distributed Evolutionary Algorithm -- Session VIII – Grid Applications and Architecture Support -- GridOS: Operating System Services for Grid Architectures -- Hierarchical and Declarative Security for Grid Applications -- A Middleware Substrate for Integrating Services on the Grid -- Performance Analysis of a Hybrid Overset Multi-block Application on Multiple Architectures -- Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors -- Keynote Address -- One Chip, One Server: How Do We Exploit Its Power? -- Session IX – Performance Evaluation and Analysis -- Data Locality Optimization for Synthesis of Efficient Out-of-Core Algorithms -- Performance Evaluation of Working Set Scheme for Location Management in PCS Networks -- Parallel Performance of the Interpolation Supplemented Lattice Boltzmann Method -- Crafting Data Structures: A Study of Reference Locality in Refinement-Based Pathfinding -- Improving Performance Analysis Using Resource Management Information -- Session X – Scheduling and Migration -- Optimizing Dynamic Dispatches through Type Invariant Region Analysis -- Thread Migration/Checkpointing for Type-Unsafe C Programs -- Web Page Characteristics-Based Scheduling -- Controlling Kernel Scheduling from User Space: An Approach to Enhancing Applications’ Reactivity to I/O Events -- High-Speed Migration by Anticipative Mobility.

9783540245964

10.1007/b94479 doi


Computer science.
Computer organization.
Microprocessors.
Software engineering.
Computers.
Algorithms.
Numerical analysis.
Computer Science.
Processor Architectures.
Software Engineering/Programming and Operating Systems.
Computer Systems Organization and Communication Networks.
Computation by Abstract Devices.
Algorithm Analysis and Problem Complexity.
Numeric Computing.

TK7895.M5

004.1

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