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Job Scheduling Strategies for Parallel Processing IPPS '97 Processing Workshop Geneva, Switzerland, April 5, 1997 Proceedings / [electronic resource] : edited by Dror G. Feitelson, Larry Rudolph. - VII, 305 p. online resource. - Lecture Notes in Computer Science, 1291 0302-9743 ; . - Lecture Notes in Computer Science, 1291 .

Theory and practice in parallel job scheduling -- Using queue time predictions for processor allocation -- A historical application profiler for use by parallel schedulers -- Memory usage in the LANL CM-5 workload -- Modeling of workload in MPPs -- PScheD Political scheduling on the CRAY T3E -- An experimental evaluation of processor pool-based scheduling for shared-memory NUMA multiprocessors -- Implementing multiprocessor scheduling disciplines -- Objective-oriented algorithm for job scheduling in parallel heterogeneous systems -- Implications of I/O for gang scheduled workloads -- Improved utilization and responsiveness with gang scheduling -- Global state detection using network preemption -- Performance evaluation of gang scheduling for parallel and distributed multiprogramming.

This book constitutes the strictly refereed post-workshop proceedings of the 1997 IPPS Workshop on Job Scheduling Strategies for Parallel Processing held in Geneva, Switzerland, in April 1997, as a satelite meeting of the IEEE/CS International Parallel Processing Symposium. The 12 revised full papers presented were carefully reviewed and revised for inclusion in the book. Also included is a detailed introduction surveying the state of the art in the area. Among the topics covered are processor allocation, parallel scheduling, massively parallel processing, shared-memory architectures, gang scheduling, etc.

9783540695998

10.1007/3-540-63574-2 doi


Computer science.
Logic design.
Microprocessors.
Architecture, Computer.
Computer programming.
Operating systems (Computers).
Algorithms.
Computer Science.
Computer System Implementation.
Operating Systems.
Programming Techniques.
Algorithm Analysis and Problem Complexity.
Processor Architectures.
Logic Design.

QA76.9.A73 QA76.9.S88

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